Publication 2018

• T. Sasao and J. T. Butler, "Decomposition of index generation functions using a Monte Carlo method," in Advanced Logic Synthesis, Springer, 2018. PDF
• I. Syafalni, T. Sasao, and X. Wen, "A method to detect bit flips in a soft-error resilient TCAM," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.37, No.6, pp.1185-1196, June 2018.
• J. T. Butler and T. Sasao, ``Analysis of the number of variables to represent index generation functions,'' B. Steinbach (e.d.) in Further Improvements in the Boolean Domain, Cambridge Scholar Publishing. PDF
• J. T. Butler and T. Sasao, "Analysis of cyclic row-shift decompositions for index generation functions," The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies" (SASIMI 2018), pp.65-70.
• T. Sasao, K. Matsuura and Y. Iguchi, "A Method to identify affine equivalence classes of logic functions," The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies" (SASIMI 2018), pp.174-179.
• I. Syafalni, K. Wakasugi, Y. Tongxin, T. Sasao and X. Wen, "Netlist conversion from costumer logic interface format (CLIF) to Verilog for legacy circuits," The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies" (SASIMI 2018), pp.180-185.
• T. Sasao, "On a memory-based realization of sparse multiple-valued functions," International Symposium on Multiple-Valued Logic, (ISMVL-2018), May 16-18, 2018, Linz, Austria, pp.50-55. PDF
• J. T. Butler and T. Sasao, "An exact method to enumerate decomposition charts for index generation functions," International Symposium on Multiple-Valued Logic, (ISMVL-2018), May 16-18, 2018, Linz, Austria, pp.138-143. PDF
• S. Nagayama,T. Sasao and J. Butler, "An exact optimization method using ZDDs for linear decoposition of index generation function," International Symposium on Multiple-Valued Logic, (ISMVL-2018), May 16-18, 2018, Linz, Austria, pp.144-149. PDF
• T. Sasao, "A logic synthesis for multiple-output linear circuits," 27th International Workshop on Logic & Synthesis (IWLS-2018), San Francisco, California, June 23-24, 2018.
• I. Safalni, T. Sasao, and X. Wen, "Bit-flip errors detection using random partial don't-care keys for a soft-error-tolerant TCAM," 27th International Workshop on Logic & Synthesis (IWLS-2018), San Francisco, California, June 23-24, 2018.
• H. Nakahara and T. Sasao, "A High-speed low-power deep neural network on an FPGA based on the nested RNS: Applied to an object detector," International Symposium on Circuits and Systems (ISCAS-2018), Florence, Italy, May 27-30, 2018, pp. 1-5.
• P. Stanica, T. Sasao, and J. T. Butler, ``Distance duality on some classes of Boolean functions,'' Journal of Combinatorial Mathematics and Combinatorial Computing, Vol. 107 on pp. 181-198, Nov. 2018.
• S. Nagayama, T. Sasao, and J. T. Butler, ``An exact optimization method using ZDDs for linear decomposition of symmetric index generation functions,'' Journal of Applied Logics-Ifcolog Journal of Logics and their Applications Vol.5, No.9, pp.1849-1866, Dec. 2018.