Publication 2016
Last Modified: April 25, 2018.
2016
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H. Nakahara, T. Sasao, H. Iwamoto, and M. Matsuura,
" LUT cascades based on edge-valued multi-valued decision diagrams: Application to packet classification,"
IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
Vol. 6, No.1, 2016, pp.73-86.
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H. Nakahara, T. Sasao, M. Matsuura, and H. Iwamoto, "An Update Method for a Low Power CAM Emulator using an LUT Cascade Based on an EVMDD (k)," Journal of Multiple-Valued Logic and Soft Computing, Vol. 26, No. 1-2, 2016, pp.109-123.
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J. T. Butler and T. Sasao,
hA set partition number system,"
Australasian Journal of Combinatorics ,
Vol. 65. No.2, 2016, pp. 152-168,
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T. Sasao,
A realization of index generation functions using multiple IGUs,"
International Symposium on Multiple-valued Logic (ISMVL-2016),
May 2016, Sapporo, Japan, pp.113-118.
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H. Nakahara, T. Sasao, H. Nakanishi, K. Iwai, T. Nagao and N. Ogawa,
"An FFT circuit using nested RNS in a digital spectrometer for a radio telescope,"International Symposium on Multiple-valued Logic (ISMVL-2016),
May 2016, pp.60-65.
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S. Nagayama, T. Sasao, and J. T. Butler,
"An efficient heuristic algorithm for linear decomposition of index generation functions,"
International Symposium on Multiple-valued Logic (ISMVL-2016),
May 2016,pp.96-101.
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D. Chowdhury, D. Das, B. Bhattacharya and T. Sasao,
"On the inadmissible class of multiple-valued faulty functions under stuck-at faults,"
International Symposium on Multiple-valued Logic (ISMVL-2016),
May 2016,pp.276-281.
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T. Sasao and J. T. Butler,
"Decomposition of index generation functions using a Monte Carlo method,"
International Workshop on Logic and Synthesis"
June. 10-11, Austin, Texas, USA.
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I. Syafalni, T. Sasao and X. Wen,
"Multiple-bit-flip detection scheme for a soft-error resilient TCAM,"
IEEE Computer Society Annual Symposium on VLSI,
Pittsburgh, Pennsylvania, U.S.A., July 11-13, 2016.
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T. Sasao, K. Matsuura, Y. Iguchi,
"A heuristic decomposition of index generation functions with many variables,"
SASIMI 2016, Kyoto, Oct. 24, 2016.
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H. Nakahara, H. Yonekawa, T. Sasao, H. Iwamoto, and M. Motomura,
"A memory-based realization of a binarized deep convolutional neural network,"
ICFPT, pp. 277-280.
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