Publication 2015

Last Modified: Oct. 16, 2015.

2015

H. Nakahara,T. Sasao, M. Matsuura, H. Iwamoto, and Y. Terao, " A Memory-based IPv6 lookup architecture using parallel index generation units," IEICE Trans. Inf. and Syst. Vol.E98-D, No. 2, pp. 262-271, Feb., 2015. PDF
H. Nakahara, H. Yoshida, S-I. Shioya, R. Mikami, and T. Sasao, "A dynamically reconfigurable mixed analog-digital filter bank: Applied to an acoustic diagnostic system," the 11th International Symposium on Applied Reconfigurable Computing (ARC-2015), April 13-17, 2015. Also, in Lecture Notes in Computer Science, Vol. , 2015, pp. . PDF
T. Sasao, "A reduction method for the number of variables to represent index generation functions: s-Min method," International Symposium on Multiple-valued Logic (ISMVL-2015), May 2015,pp.164-169. PDF
H. Nakahara,T. Sasao, H. Nakanishi, and K. Iwai, "An RNS FFT circuit using LUT cascades based on a modulo EVMDD," International Symposium on Multiple-valued Logic (ISMVL-2015), May 2015,pp.97-102. PDF
S. Nagayama, T. Sasao, J T. Butler, M. Thornton, and T. Malikas, "Edge reduction for EVMDDs to speed up analysis of multi-state systems," International Symposium on Multiple-valued Logic (ISMVL-2015), May 2015, pp.170-175. PDF
T. Sasao, "On the sizes of reduced covering tables for incompletely specified index generation functions," Reed-Muller 2015, May 21, 2015, Waterloo, Ontario, Canada. PDF
R. S. Stankovic, T. Sasao, and J.T. Astola, "Contributions of Yasuo Komamiya to switching theory," Reed-Muller 2015, May 21, 2015, Waterloo, Ontario, Canada. PDF
I. Syafalni, T. Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase, "Soft-error tolerant TCAM using partial don't-care keys," 20th IEEE European Test Symposium, May 25-29, 2015, Cluj-Napoca, Romania. PDF
T. Sasao, I. Fumishi, and Y. Iguchi, "A method to minimize variables for incompletely specified index generation functions using a SAT solver," International Workshop on Logic and Synthesis, Mountain View, June 12-13, 2015, pp.161-167. PDF
I. Syafalni, T. Sasao, and X. Wen, "A soft-error tolerant TCAM for multiple-bit flips using partial don’t-care keys," International Workshop on Logic and Synthesis, Mountain View, June 12-13, 2015, pp.11-18. PDF
H. Nakahara and T. Sasao, "A deep convolutional neural network using nest residue number system," 25th International Conference on Filed-Programmable Logic and Applications (FPL2015), Sept. 2-4, 2015, London, United Kingdom,pp.1-6. PDF
T. Sasao, "Index generation functions: Logic synthesis for pattern matching," EPFL Workshop on Logic Synthesis and Verification," Dec. 10-11, Lausanne, Switzerland (invited). PDF

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