Publication 2004

• D. Debnath and T. Sasao, "Fast Boolean matching under permutation by efficient computation of canonical form," IEICE Transactions on Fundamentals of Electronics, Vol.E87-A, Dec. 2004, pp.3134-3140. PDF
• H. Qin, T. Sasao, M. Matsuura, K. Nakamura S. Nagayama and Y. Iguchi "A realization of multiple-output functions by a look-up table ring," IEICE Transactions on Fundamentals of Electronics, Vol.E87-A, Dec. 2004, pp.3141-3150. PDF
• H. Nakahara, T. Sasao, and M. Matsuura, "A design algorithm for sequential circuits using LUT rings," The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2004), Oct. 18-19, 2004, Kanazawa, Japan, pp.430-437. PDF
• T. Sasao, J. T. Butler, and M. D. Riedel, "Application of LUT cascades to numerical function generators," The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2004), Oct. 18-19, 2004, Kanazawa, Japan, pp.422-429. PDF
• T. Sasao, H. Nakahara, M. Matsuura and Y. Iguchi, "Realization of sequential circuits by look-up table ring," The 2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, July 25-28, 2004, pp.I:517-I:520. PDF
• B. Falkowski and T. Sasao, "Implementation of Walsh function generator of order 64 using lut cascades," The 2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, July 25-28, 2004, pp.III:447-III:450. PDF
• T. Sasao and M. Matsuura, "A method to decompose multiple-output logic functions," 41st Design Automation Conference, San Diego, CA, USA, June 2-6, 2004, pp.428-433. PDF
• T.Sasao, M. Kusano, and M. Matsuura, "Optimization methods in look-up table rings," International Workshop on Logic and Synthesis (IWLS-2004), June 2-4, Temecula, California, U.S.A. .pp. 431-437. PDF
• S. Nagayama and T. Sasao, "On the minimization of longest path length for decision diagrams," International Workshop on Logic and Synthesis (IWLS-2004), June 2-4, Temecula, California, U.S.A., pp. 28-35. PDF
• S. Nagayama and T. Sasao, "On the minimization of average path lengths for heterogeneous MDDs," 34th International Symposium on Multiple-Valued Logic (ISMVL-2004), Toronto, Canada, May 19-22, 2004, pp. 216-222. (Outstanding Contributed Paper Award presented at ISMVL2005). PDF
• Y. Iguchi, T.Sasao, and M. Matsuura, "A method to evaluate logic functions in the presence of unknown inputs using LUT cascades," 34th International Symposium on Multiple-Valued Logic (ISMVL-2004), Toronto, Canada, May 19-22, 2004, pp. 302-308. PDF
• S. Nagayama, T. Sasao, Y. Iguchi, and M. Matsuura, "Area-time complexities of multi-valued decision diagrams," IEICE Transactions on Fundamentals of Electronics, Vol.E87-A, No.5, pp. 1020-1028, May, 2004. PDF
• A. Iseno, Y. Iguchi, and T. Sasao, "Fault diagnosis for RAMs using Walsh spectrum," IEICE Trans. Information and Systems, Vol. E87-D, No.3, March 2004, pp. 592-600. PDF
• T. Sasao,"Survey of research projects conducted by Sasao's group," (draft) Jan 26, 2004. PDF
• T. Sasao and Jon T. Butler, "A fast method to derive minimum SOPs for decomposable functions," ASP-DAC 2004 (Asia and South Pacific Design Automation Conference 2004), Yokohama, Jan. 27-30, 2004, pp. 585-590. PDF
• D. Debnath and T. Sasao, " Efficient computation of canonical form for Boolean matching in large libraries," ASP-DAC 2004 (Asia and South Pacific Design Automation Conference 2004), Yokohama, Jan. 27-30, 2004, pp. 591-596. PDF
• S. Nagayama and T. Sasao, "Minimization of memory size for heterogeneous MDDs," ASP-DAC 2004 (Asia and South Pacific Design Automation Conference 2004), Yokohama, Jan. 27-30, 2004, pp. 872-875. PDF