Publication 1999

• Hafiz Md. Hasan Babu and T. Sasao, "Representations of multiple-output functions using binary decision diagrams for characteristic functions," IEICE Trans. Fundamentals, Vol. E82-A, No.11, pp. 2398-2406, Nov. 1999. PDF
• T. Sasao, "Arithmetic ternary decision diagrams and their applications," Fourth International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, (Reed-Muller 99), Victoria, Canada, August 20-21, 1999. PDF
• D. Debnath and T. Sasao, "Exact minimization of FPRMs for incompletely specified logic functions," Fourth International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, (Reed-Muller 99), Victoria, Canada, August 20-21, 1999. PDF
• T. Sasao and S. Kajihara, "Functional decompositions using an automatic test pattern generator and a logic simulator," ACM/IEEE International Workshop on Logic Synthesis, Lake Tahoe, CA, June 1999. PDF
• Hafiz Md. Hasan Babu and T. Sasao, "Time-division multiplexing realizations of multiple-output functions based on shared multi-terminal multiple-valued decision diagrams," IEICE Trans. Information and Systems, Vol. E82-D, No. 5, pp. 925-932, May 1999. PDF
• T. Sasao, "Totally undecomposable functions: applications to efficient multiple-valued decompositions," IEEE International Symposium on Multiple-Valued Logic, Freiburg, Germany, May 20-23, 1999, pp. 59-65. PDF
• Hafiz Md. Hasan Babu and Tsutomu Sasao, "Shared multiple-valued decision diagrams for multiple-output functions," IEEE International Symposium on Multiple-Valued Logic, Freiburg, Germany, May 20-23, 1999, pp. 166-172.
• D. Debnath and T. Sasao, "Multiple-valued minimization to optimize PLA with output parity gates," IEEE International Symposium on Multiple-Valued Logic, Freiburg, Germany, May 20-23, 1999, pp. 99-104. PDF
• T. Sasao, Switching Theory for Logic Synthesis, Kluwer Academic Publishers, 1999. Outline
• T. Sasao, "On a method to accelerate functional decompositions," Dagstuhl Seminar, Jan. 26, 1999.
• Y. Iguchi, T. Sasao, M. Matsuura, and A. Iseno, "Realization of regular ternary logic functions using double-rail logic," Asia and South Pacific Design Automation Conference, ASP-DAC'99, Jan. 1999. pp. 331-334. PDF
• D. Debnath and T. Sasao, "Fast Boolean matching under variable permutation using representative," Asia and South Pacific Design Automation Conference, ASP-DAC'99, Jan. 1999. pp. 359-362. PDF