Publication 1995
1995
- T. Sasao: Logic Design: Switching Circuit Theory,
(in Japanese) Kindai Kagaku Publishing Company (1995-01).
- T. Sasao and J. T. Butler, "Planar Multiple-Valued Decision Diagrams,"
IEEE International Symposium on Multiple-Valued Logic,
Bloomington, Indiana, May 23-25, 1995, pp. 28-35.
(Distinguished Contributed Paper Award presented at ISMVL1996).
- T. Sasao, "A design method for AND-OR-EXOR three-level networks,"
ACM/IEEE International Workshop on Logic Synthesis,
Tahoe City, California, May 23-26, 1995, pp.8:11- 8:20.
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- T. Sasao, "Representation of logic functions using EXOR operators,"
IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansions in
Circuit Design (Reed-Muller '95), Makuhari, Japan. Aug. 27-29, 1995.
- R. S. Stankovic, T. Sasao, and C. Moraga, "Spectral transforms decision
diagrams," IFIP WG 10.5 Workshop on Applications of the Reed-Muller
Expansions in Circuit Design (Reed-Muller '95), Makuhari, Japan. Aug.
27-29, 1995.
- N. Koda and T. Sasao, "An upper bound on the number of products in minimum
ESOPs," IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansions
in Circuit Design (Reed-Muller '95), Makuhari, Japan. Aug. 27-29, 1995.
- T. Sasao, H. Hamachi, S. Wada and M. Matsuura, "Multi-level logic synthesis based on pseudo-Kronecker decision diagrams and logical transformation,"
IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansions in
Circuit Design (Reed-Muller '95), Makuhari, Japan. Aug. 27-29, 1995.
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- T. Sasao and F. Izuhara, "Exact minimization of AND-EXOR expressions
using multi-terminal EXOR ternary decision diagram,"
IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansions in
Circuit Design (Reed-Muller '95), Makuhari, Japan. Aug. 27-29, 1995.
- D. Debnath and T. Sasao, "GRMIN: A heuristic minimization algorithm for
generalized Reed-Muller expression," IFIP WG 10.5 Workshop on Applications
of the Reed-Muller Expansions in Circuit Design (Reed-Muller '95),
Makuhari, Japan. Aug. 27-29, 1995.
- D. Debnath and T. Sasao, "GRMIN: A heuristic minimization algorithm for
generalized Reed-Muller expression,"
Asia and South Pacific Design Automation Conference (ASPDAC'95),
Aug. 29-Sept. 1, Makuhari, Japan, pp. 341-347.
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