Publication 1994

1994

J. T. Butler and T. Sasao, "Multiple-valued combinational circuits with feedback," IEEE ISMVL-94, May 1994, pp. 342-347.
T. Sasao and J. T. Butler, "A design method for look-up table type FPGA by pseudo-Kronecker expansion" IEEE ISMVL-94, May 1994, pp. 97-106. PDF
R. S. Stankovic, M. Stankovic, C. Moraga, and T. Sasao, "The calculation of Reed-Muller coefficients of multiple-valued functions through multi-place decision diagrams," IEEE ISMVL-94, May 1994, pp. 82-88.
T. Sasao, "Logic design of FPGAs"(in Japanese), Jo-Ho-Shori, Vol. 35, No. 6, pp. 530-534, June 1994.
T. Sasao, "Easily testable realization for generalized Reed-Muller expressions," IEEE The 3rd Asian Test Symposium, November 15-17, 1994, Nara Japan, pp. 157-162.
T. Sasao and D. Debnath, "An exact minimization algorithm for generalized Reed-Muller expressions," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'94) December 5-8, 1994, Taipei, Taiwan, pp. 460-465.
N. Koda and T. Sasao, ``A minimization method for AND-EXOR expressions using lower bound theorem,'' Systems and Comuter in Japan, Vol.24, No.13, 1994. (English Translation of KODA_IEICE1993.) PDF